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ABSTRACTS

 

Title:  

Welcome and Opening Remarks

Speaker:  

Bahgat Sammakia, Interim Vice President for Research, the New York State Center of Excellence in Small Scale Systems Integration and Packaging

Presentation:  

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Title:  

The New Dynamics of the Semiconductor Business

 Abstract:   The presentation entitled "The New Dynamics of Semiconductor Business." is to explore long term trends and the current characteristics of industry growth, as well as the effect of increasing capital expenditure and R&D investment. He would discuss ongoing industry consolidation, business fundamentals, and sought to identify the new dynamics, which are creating opportunities across the broad spectrum of companies within the semiconductor business community. And, the unique value of packaging would be highlighted from a business perspective.
Speaker:  

Tien Wu

Bio(TBA)

Presentation:  

For presentation click here.

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 Title:  

Advanced Electric Powe r Systems -- Key Concepts and Technologies.

 Abstract:   Future electric system will be power electronic systems. A new generation of packaging is needed for higher voltage and higher power electronic systems. New control concepts are needed for an integrated system of many power electronic converters. Power systems with bi-directional converters are needed to rapidly redirect and recover power. The reasoning for these needs will be presented. Some of the key concepts, technologies, and research needs will be discussed.
Speaker:  

Terry Ericsen

Mr. Terry Ericsen is a Program Officer for Electrical Science and Technology for the Office of Naval Research. Mr. Ericsen has worked for the Navy from 1970 to present in many engineering assignments from Cooperative Education Student to Program Officer. Mr. Ericsen has been the Principle Investigator on many diverse technology development programs ranging from power semiconductor device, power semiconductor packages, circuits, control, and power electronic equipment. Mr. Ericsen managed the Navy's highly successful Power Electronic Building Block program which has led to the present Medium Voltage DC architecture concepts under investigated for future ships. Mr. Ericsen graduated from the George Washington University with a BS in Electrical Engineering in 1973.

Presentation:  

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 Title:   Stacked IC Packaging with TSV – True 3D without the Glasses
     
 Abstract:   Stacked 3D IC packaging using through silicon vias (TSVs) promises to provide a quantum leap to system in package (SiP) implementations with respect to power, performance and size ("More than Moore"). By increasing system level functionality, it could provide an alternative path when lithographical scaling hits fundamental limits or becomes prohibitively expensive ("More Moore"). Compared to other industry transitions, 3D-IC packaging impacts a wider range of the supply chain, from design to wafer fabrication, packaging and test. SEMATECH is at the epicenter of this transition, and we will outline how research, government and industry collaboration must come together to make this technology transition successful.
Speaker:  

Klaus Hummler

Klaus Hummler received MS and Ph.D. degrees in physics from the University of Stuttgart and the Max-Planck-Institute in Stuttgart, Germany. After joining Siemens Microelectronics he spent 15 years in the memory industry in areas of process development, product- and systems engineering, and test. One of his key technical achievements was the introduction of KGD testing for stacked-die mobile DRAM products at Infineon. Before joining SEMATECH, Dr. Hummler developed TSV interposer technology for so-called "2.5D integration" at a start-up company in North Carolina.
Dr. Hummler is now managing the department "3D Integration, Test Vehicles, and Reliability" at the 3D Interconnect division of SEMATECH.

Presentation:  

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 Title:   Advanced Package Trends - From LED to MPU
     
 Abstract:  

This Presentation will outline key trends in Advanced Packaging across a range of devices and package types. Key high level trends in LEDs (package vs module), flip chip (Cu Pillar and Underfill), 3D (PoP and stacked die), and wafer level solutions will be discussed. 

 Speaker:   BRANDON PRIOR
Senior Consultant
Prismark Partners

Brandon joined Prismark in 1996 and has been the primary author and editor of Prismark's Semiconductor and Packaging Quarterly Report since 2000. His research focuses on all aspects of packaging solutions, from MEMs and LED to advanced 3D approaches. Brandon provides research and insight to leading IDMs, OSATs, foundries, material suppliers and equipment manufacturers.

Brandon Prior has BA and BE degrees from Dartmouth College and the Thayer School of Engineering in Hanover NH.

Presentation   For presentation click here.
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Title:   Extremely Energy Efficient Chiller-less Data Centers Using Liquid Cooled Servers
     
 Abstract:   Information  Technology  (IT)  data  centers  consume  a  large  amount  of electricity in the US and world-wide.  Cooling has been found to contribute about  one third of this energy use.  Thus, understanding and improving the thermal  management  and  energy  efficiency  of  data center systems is of growing importance from a societal cost and sustainability perspective.  In addition  to  their energy consumption related challenges, the heat flux of electronic devices and the volumetric heat density of servers and the racks that  house  them are also rapidly increasing for many applications.  Thus, research  and  productized  technologies that enhance energy efficiency and cooling  performance  over  several length scales of electronic devices and systems  will  be  critical to the future success of the IT industry.  This
presentation  summarizes  part  of  an  US Department of Energy cost shared grant,  two  year  IBM  project  (2010-2012) that was undertaken to develop highly  energy efficient warm liquid cooled servers for use in chiller-less data  centers that could save significant data center energy use and reduce data  center  refrigerant  and  make up water usage.  The objective of this project  is  to  reduce  the  cooling  energy to 5% or less of a comparable typical  air  cooled  chiller  based  total data center.  Additional energy savings  can  be  realized  in  reducing  the  IT rack power itself through reduced server fan power and lower leakage power at the  microprocessors due to lower device temperatures on average for many locations.
 Speaker:  

Madhu Iyenagar

Dr. Madhusudan Iyengar is a Senior Engineer at the IBM Poughkeepsie Advanced Thermal Laboratory, working on energy efficient cooling technologies for servers and data centers. He received his BE in Mechanical Engineering from the University of Pune, India in 1994, and his PhD in Mechanical Engineering from the University of Minnesota in 2003. He is a member of ASME, IEEE, ASHRAE, and IMAPS. He has co-authored over 95 technical papers in journals and conferences, three book chapters, and holds 84 issued US patents. In 2009, he was awarded the IEEE-CPMT Outstanding Young Engineer Award for cutting edge cooling technology and product development with realizable benefits to the IT industry and its' customers. He currently serves as a Guest Editor for the IEEE Transactions on Components and Packaging Technologies and is the Chair for the "Thermal Management" Track for the the 2012 IEEE ITherm Conference.

Presentation:  

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Title:  

Energy Efficient Thermal Management of Data Centers Via Reduced Order Modeling Based Design

     
 Abstract:   The heat generated by the electronic equipment and the costs of powering the cooling systems in data centers are increasing continually. Real time energy efficient design of these systems requires quick but still accurate thermal modeling approaches. In this presentation, new Proper Orthogonal Decomposition (POD) based reduced order thermal modeling method is presented to simulate multi-parameter dependent temperature field in complex convective systems such as data centers. The methods results in average error norm of ~ 6%, while it can be up to ~250 times faster than CFD/HT simulation in an iterative optimization technique. The POD method is used along with optimization techniques for designing an energy efficient air cooled data center cell with an annual increase in the power consumption. The optimization results in a 12-46% reduction in the energy consumption of the center in addition to being adjustable to the newer IT equipment and higher heat loads, compared with a traditional design. Also, the POD based modeling and power profiling of IT equipment is used to bring adaptability for coordinated minimization of cooling and IT power consumption in future open data centers. This coordination results in 12-70% saving in the total energy consumption of a data center cell in different scenarios.
 Speaker:  

Emad Samadiani

Emad Samadiani is a visiting research assistant professor at Binghamton University, working in Small Scale Systems Integration & Packaging Center. He received his PhD in Mechanical Engineering from Georgia Institute of Technology in August 2009, under the guidance of Prof. Yogendra Joshi. Before joining BU, he was a post-doctoral fellow at Georgia Tech. His research interests are in computational and reduced order modeling methods for energy efficient electronics and data center thermal management at various scales. He has co-authored over 15 journal and peer reviewed conference papers, one of which has received best-paper award from ASME. 
Presentation:  

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Title:   Packaging and integration of advanced phase-change heatspreaders for high performance electronics
     
Abstract:   The dramatic increase in power densities in high performance electronics over the last decade has led to various thermal bottlenecks that require advanced thermal management solutions. A significant part of the system-level thermal resistance budget is commonly taken up by the spreading/conduction resistances in the thermal network. In this context, two-phase cooling solutions via planar heatpipes and heatspreaders appear promising due to their ability to transport/spread heat with very low thermal resistance, as compared to conventional solid conduction-based heat dissipation.

This talk will describe the design, fabrication and thermal performance characteristics of planar phase-change heatpipe/heatspreaders for high heat flux electronics cooling applications. Key aspects of heatpipe fabrication technology including wick fabrication, edge sealing and fluid charging are described. A key parameter for reliable, high performance heatpipes is the design and fabrication of micro-porous wick structure. In this paper, various wick fabrication methods are described and compared via experimental testing. The methods are compared based on thermal characteristics of the wick and wick-substrate interface, effective pore size and porosity measurements, chemical stability in aqueous environments and the thermal performance of fully packaged heatpipes. The talk will also describe the contribution from various component resistances i.e. solid conduction and phase-change resistances for evaporation/condensation, to the overall thermal performance of heatpipes. The importance of new breakthroughs in evaporation/condensation heat transfer to further reduce phase change resistances in order to enhance the impact of this technology in electronics cooling will be highlighted.

Speaker:  

Shakti Chauhan

Dr. Shakti Chauhan received his Ph.D. in Materials Science from Iowa State University prior to joining GE in 2008. Dr. Chauhan's technical background involves aspects of both material science and mechanics, including plastic deformation mechanisms at micro/nano length scales, fracture mechanics and material systems for high performance thermal management applications. At GE Global Research, Dr. Chauhan has worked on developing packaging and thermal management solutions for photovoltaics, power electronics and high reliability military systems.

Presentation:  

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 Title:   Integrated EMI Shielding Technologies for RF Applications
     
Abstract:   TBA
 Speaker:  

Yifan Guo

Bio(TBA)

Presentation:  

For presentation click here.

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Title:   Miniaturization in Electronic Packaging or Thin is In
     
Abstract:   The relentless march of miniaturization of electronic products is continuing unabated as evidenced by iPods, iPhones, iPADs, etc. Yet at the same time more functionality is added to the products in a shrinking product volume. This dichotomy is solved only in part by silicon integration and software, packaging has become a key contributor to solving this challenge. Examples of substrate and package challenges and solutions will be presented along with some changes in business models.
Speaker:  

Bernd Appelt

Bernd Appelt received his PhD in Polymer Science at the University of Mainz, Germany. Subsequently he worked at IBM for 23 years in materials development and characterization. He also held management position in Development and Manufacturing Engineering.   In 2003 Bernd joined ASE and currently is Director of Business Development with a focus on organic substrate and assembly technologies. He holds more than 50 patents and has authored nuemrous papers and book chapters.

Presentation:  

For presentation click here.

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 Title:   Wafer Level Underfill for Fine Pitch, Small Gap, Flip Chip Organic Packages
     
 Abstract:   The continuing trend to increase function and reduce size presents opportunities for new material and process development.   One such opportunity is in flip chip packaging as the solder joint size, pitch and underfill gap decrease.   It is a challenge to effectively and efficiently clean under the chip after solder attach. Formulating capillary underfills for smaller gaps requires the use of smaller particles so that flow in the small gap is possible.   However, this can result in an increase in viscosity due to the increased surface area from smaller particles that still have to be present at a similar filler weight percent to achieve the target cured properties. Capillary underfilling is an inherently slow process. Wafer level underfill, applied either on the wafer before dicing or after dicing onto individual chips, overcomes the need to clean flux residues after the flip chip is attached. Also, wafer level underfill eliminates the constraints of capillary flow processes.   However, there are significant new challenges in formulating wafer level underfills and developing the processes for deposition and bonding. After the wafer level underfill is applied, cure advancement must be slow or dormant so that there is a manufacturable shelf life until the chips are attached. Transparency is required in the coating of underfill over the solder joints so that alignment is possible between the chip and substrate. The bonding process cycle must be rapid to be competitive with traditional in-line reflow processing. The yield on solder interconnection must be 100%. The resulting cured underfill must have the material attributes and properties to ensure solder joint reliability and preserve chip structure integrity. Significant progress has been made in developing wafer level materials and processes that achieve 100% solder joining. The solder joint reliability is maintained throughout a battery of environmental stress tests.
 Speaker:  

Michael Gaynes

Michael Gaynes joined IBM in 1979 with a BS in Chemical Engineering from Brigham Young University. He has held technical leadership positions that cover a wide spectrum of electronic packaging in manufacturing and development.   These include ceramic chip carrier circuitization, failure analysis, reliability test and model development, flip chip organic packaging design and process development, adhesive development and adhesion science. From 1990 to 2003, he directed materials and process development efforts for applications that require thermally and electrically conductive adhesives, die attach adhesives and flip chip underfills. He joined IBM Research in 2003 and is providing leadership in developing advanced adhesive solutions that are needed for next generation electronic packages. Michael is a Senior Technical Staff Member with 32 technical publications and over 100 US patents issued.

Presentation:  

For presentation click here.

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 Title:   Importance of Die to Package Interactions for MEMS
     
 Abstract:   TBA
Speaker:  

Carl Raleigh

Carl Raleigh received a Ph.D. degree in Chemistry from Texas A&M University. During his career he has been a Professor at Drake University, has started multiple technical groups in Motorola, was a Director of Global Technical Operations at On Semiconductor, and has consulted in packaging and assembly for a number of companies. He has published more than 20 Papers and holds 9 patents. He has been working at ADI since 2006 developing MEMS packaging.
Presentation:  

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 Title:   Bio-molecule Integration for Sensors and Diagnostic Devices
     
 Abstract:   TBA
 Speaker:  

Ralf Lenigk

Bio(TBA)

Presentation:  

For presentation click here.

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 Title:   Micro Packaging Technologies for MEMS and Integrated Microsystems
     
 Abstract:   The Center for Wireless Integrated MicroSystems (WIMS) at the University of Michigan has concentrated in two different areas of MEMS packaging: implanted biomedical device packaging and wafer bonding. In the wafer bonding area we have developed new methods of bonding substrates together. These techniques include field assisted gold silicon eutectic and parylene based wafer bonding among others. In the biomedical device area, we have applied these techniques and others to create biocompatible implanted devices that resist decades of implantation in the body. Some example technologies include multilayer gold parylene thin film shells to protect circuitry and galvanic biasing to prevent polysilicon from being dissolved by the body.
Speaker:  

Andrew Oliver

Andrew "Andy" Oliver received the B.S.E.E. degree with distinction from Iowa State University, Ames, Iowa, in 1991 and the M.S.E.E. and Ph.D. in Electrical Engineering from the University of Michigan, Ann Arbor, Michigan, in 1993 and 1997, respectively. In 1997, he joined Sandia National Laboratories in Albuquerque, New Mexico, where he worked on the design, fabrication, and packaging of surface micromachines. He joined ICx Ion Optics in Waltham, Massachusetts in 2006, where he designed infrared based gas detectors and developed wafer-level vacuum packages for MEMS devices. In 2011, he joined the University of Michigan's Center for Wireless Integrated Microsystems as the Industrial Outreach Coordinator. Andy is a recipient of an R&D 100 award for one of the 100 most technology significant new products of 2008, has one patent, and has authored 8 journal papers, 5 book chapters, and more than 20 conference papers.

Presentation:  

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 Title:   Ones size doesn't fit all
     
 Abstract   Monolithic to multi die, applications are becoming so diverse, many design approaches are required to leverage innovation in MEMS structure design and the signal processing needed to optimize performance, size and cost. Requests for total heterogeneous solutions are more frequent, however full integration is not always the optimal solution.
 Speaker:  

Rob O'Reilly

Rob joined the Analog Devices MEMS team at the outset of MEMS development and has spent the last 20 years developing test, characterization and reliability flows for accelerometer, gyro and microphone products. Currently Rob is responsible for assessing advanced test needs, as well as unique business and applications for inertial MEMS devices. A former flight engineer in the US Navy, Rob attended Northeastern University studying solid state physics and mechanical engineering.

Presentation:  

For presentation click here.

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 Title:   Ni/Sn Transient Liquid Phase Bonding Technology for High Temperature Operational Vehicle Application
     
Abstract:   This talk presents the demonstration of nickel-tin transient liquid phase (Ni/Sn TLP) bonding in power electronics application. High temperature operational power electronics are urgently demanded for power electronics in electrified vehicles (Hybrid Electric, Plug-in Hybrid, and Electric Vehicles). The high temperature operation yields substantial challenges in packaging and attachment technology. TLP bonding is one approach that addresses these challenges and thus secures high reliability. Especially, the Ni/Sn TLP enables numerous design characteristics for automotive applications including a good CTE match with Si and SiC, popularity in conventional power electronics, low cost, and uniform alloy formation. This work demonstrates a Ni/Sn TLP bonding technology for high temperature operation as applied to large size silicon power devices. Analysis indicates that the resulting bondline is uniformly composed of Ni3Sn4 alloy throughout. Excellent reliability for bonded devices was exhibited after thermal cycles from -40 to 200 degC.
Speaker:  

Dr. Sang Won Yoon

Sang Won Yoon received the B.S. degree from the Department of Electrical Engineering, Seoul National University, Seoul, Korea, in 2000, and the M.S. and Ph.D. degrees from the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, in 2003 and 2009, respectively. Since 2009, he has been with Toyota Research Institute of North America, USA, and focusing on development of power systems and sensor systems for future electrified vehicles. From 2002 to 2008, he developed wireless sensor systems and environment-resistant packaging technologies for microelectromechanical systems (MEMS) at the Center of Wireless Integrated Microsystems. His research interests include the analysis, design, fabrication, and testing of MEMS/NEMS and packaging technologies, sensor systems, and power electronics/modules for automotive applications. Dr. Yoon was the recipient of the Information and Technology National Fellowship from the Korean Ministry of Information and Communication.

Presentation:  

For presentation click here.

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Title:   High Temperature Silicon Carbide Power Modules for High Performance Systems
     
 Abstract:   The demands of modern high-performance power electronics systems are rapidly surpassing the power density, efficiency, and reliability limitations defined by the intrinsic properties of silicon-based semiconductors. The advantages of silicon carbide (SiC) are well known, including high temperature operation, high voltage blocking capability, high speed switching, and high energy efficiency. In this discussion, APEI, Inc. presents two newly developed high performance SiC power modules for extreme environment systems and applications. These power modules are rated to 1200V, are operational at currents greater than 100A, can perform at temperatures in excess of 250 °C, and are designed to house various SiC devices, including MOSFETs, JFETs, or BJTs.

One newly developed module is designed for high performance, ultra-high reliability systems such as aircraft and spacecraft, and features a hermetically sealed package with a ring seal technology capable of sustaining temperatures in excess of 400°C. The second module is designed for high performance commercial and industrial systems such as hybrid electric vehicles or renewable energy applications, implements a novel ultra-low parasitic packaging approach that enables high switching frequencies in excess of 100 kHz, and weighs in at just over 130 grams (offering ~5× mass reduction and ~3× size reduction in comparison with industry standard power brick packaging technology). It is configurable as either a half or full bridge converter.

Speaker:  

Jared Hornberger

Jared Hornberger is part owner and a board member at Arkansas Power Electronics International, Inc. (APEI, Inc.). Mr. Hornberger joined APEI, Inc. in 2002 and currently manages and leads the electronics packaging activities and is the Director of Manufacturing. He received his Bachelor and Master of Science in Electrical Engineering at the University of Arkansas in 2002 and 2004 respectively. Mr. Hornberger's expertise lies in the design and development of state-of-the-art power electronics packaging technologies focusing on high temperature, high power density, and SiC     power electronics systems.

Presentation:  

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 Title:   Thermal Management and Reliability of Power Electronic Systems
     
Abstract:   With the increasing power densities of modern power electronic systems, it is critical to performance and reliability to be able to remove the large heat flux generated to ensure the junction temperature of the devices remain in an allowable range. This presentation will compare and contrast some of the proposed single and two-phase thermal management solutions and provide data on their ability to provide uniform cooling for power electronic systems.
Speaker:  

Patrick McCluskey

Patrick McCluskey is an Associate Professor of Mechanical Engineering at the University of Maryland, College Park where he is associated with the CALCE Center. He is currently on joint appointment with the National Renewable Energy Laboratory leading efforts on advanced power electronics thermal management and reliability. He has published extensively in the area of packaging and reliability of electronics and microsystems for high power and extreme temperature environments, including three books and numerous book chapters. He has also served as general or technical chairman for numerous conferences in these research areas.   Dr. McCluskey is an associate editor of the IEEE Transactions on Components and Packaging Technologies.

Presentation:  

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Title:    Novel ACA as a Lead-free Alternative for small form factor and 3D Packaging
     
Abstract:    TBA 
 Speaker:   S. Manian Ramkumar 
Presentation:   For presentation click here.
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Title:   Packaging Technologies for 500C SiC Electronics and Sensors
     
Abstract:   TBA 
Speaker:  

Dr. Liangyu Chen

Liang-Yu Chen received his Pd.D. degrees in experimental solid state physics from Case Western Reserve University, Cleveland, Ohio, in 1994. Currently, he is a Senior Scientist at Ohio Aerospace Institute, and supports the high temperature electronic packaging research program at NASA Glenn Research Center. His major research interests include materials, structure, process, and testing of packaging technologies for silicon carbide electronics and sensors for applications in high temperature harsh environment.

Presentation:  

For presentation click here.

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 Title:   Substrate and Silicon Carbide (SiC) Packaging Technologies for 300°C Application
     
Abstract:   Economic geothermal well construction and reservoir characterization requires high temperature logging tools and sensors with the long-term operation capability of 300°C. However, to build functional circuits, an interconnection and packaging technology must be demonstrated to provide interconnectivity between different SiC devices and passive components. Thick film based ceramics, and multilayer thin film ceramic technologies make them the potential candidates for addressing the needs. In this work, the following studies are included: 1) the effect of 300°C storage on the adhesion of different thickfilm gold (Au) conductors and multilayer dielectric for thickfilm-alumina technology; 2) thickfilm Au adhesion on low temperature cofired ceramic (LTCC) substrate under 300°C aging, via reliability on the multilayer LTCC substrate under temperature cycling of 35-325°C; 3) thin film conductor metallization and dielectrics on aluminum nitride (AlN) substrate process development and testing; 4) SiC device wire bonding and flip chip packaging; 5) external leads attaching.
Speaker:  

Tan Zhang

Tan Zhang received the B.S. and M.S. degrees in materials engineering from Beijing University of Aeronautics and Astronautics, Beijing, China, in 1996 and 1999, and the Ph.D. degree in electrical engineering from Auburn University, Auburn, AL, in 2006. She is currently an Electronics Packaging Engineer with GE Global Research Center, Niskayuna, NY. Her current research includes CZT crystal defects inspection and packaging, high-temperature electronics, and Pb-free solder process development and failure analysis.

Presentation:  

For presentation click here.

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Title:   Role of Alloying Elements in High-Temperature Solders
     
Abstract:   Electronics and sensors for oil and gas downhole drilling and next generation power semiconductor devices will experience higher temperature environments than conventional electronics. Therefore, a careful selection of materials and their microstructures are required to ensure the reliable service of such devices at high temperatures (>200˚C). The solder alloys are considered for passive interconnects and die attach materials, for which high Pb-content solders (over 85%) fit favorably to melting temperatures (Tm) in the range of 255-313˚C. Alloying elements such as Sn, In, Sb, and Ag can not only adjust melting temperatures, but also tailor microstructures thereby improving mechanical properties. A high Sn-content solder was also chosen for Pb-free potentials in this study. In particular, 85Pb-10Sb-5Sn exhibited very interesting superplastic behavior (over 1100% strain) at certain conditions. In this presentation, microstructure features and the relationship to mechanical properties, along with relevant constitutive parameters and new directions for alloy development, will be highlighted.
Speaker:  

Junghyun Cho

Dr. Junghyun Cho is currently an associate professor and a director of Graduate Studies in the Department of Mechanical Engineering and a director of the Materials Engineering Program at the State University of New York (SUNY) at Binghamton. He joined the University as an assistant professor in Fall 2001 after finishing a postdoctoral research appointment at the University of California, Santa Barbara. He received his B.S. in Metallurgical Engineering from Yonsei University (Seoul, Korea) in 1991, M.S. in Materials Science and Engineering from Northwestern University in 1993, and Ph.D. in Materials Science and Engineering from Lehigh University in 1998. Before starting his graduate studies, Dr. Cho had worked at Samsung Semiconductor R&D Center (Kihung, Korea) in the area of electronics packaging materials and processes (1990-91). His research interests include microstructure design of advanced materials, ceramic thin films, processing science, and mechanical behavior of materials.

Presentation:  

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Title:    Meeting the High Power Density Thermal Management Challenges for Future High Performance Computing
     
Abstract:    TBA
Speaker:   

How Lin

How T. Lin holds Ph. D. degree in Electrical Engineering from Rensselaer Polytechnic Institute, MSEE and BEE degrees from Georgia Institute of Technology. From 1977 to 2001, he was responsible for developing advanced precisions artwork generators utilizing massively parallel graphics processors and novel high-speed process equipments at IBM. He is the Chief Scientist/Systems Architect at Endicott Interconnect Technologies since 2001. Dr. Lin is responsible for developing high performance computing architectures and flexible custom accelerator systems for HPC applications. His current research focus are in high speed electrical/optical interconnects, electronic/
electro-optical packaging technologies and largescale custom supercomputing systems. He has received three IBM Outstanding Innovation/Achievement Awards and 43 US patents. His publications included more than 30 journal articles, 20 conference papers and 2 book chapters. 
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Title:  

 3D TSV Interconnect Technology: Process Challenges for High Volume Manufacturing

     
Abstract:   The promise of stacked 3D IC packaging using through silicon vias (TSVs) to deliver system improvements with respect to power, performance and size ("More than Moore") depends critically on a viable path to high volume manufacturing. Independent of 3D process integration schemes, many common process and tooling gaps need to be addressed before this technology can be broadly adopted. SEMATECH shares its perspective on these gaps with a special emphasis on bonding methodologies.
Speaker:  

Roger Quon

Roger A. Quon
SEMATECH International, Albany, NY
IBM Semiconductor Research and Development Center, East Fishkill, New York

Roger Quon is on assignment from IBM to lead SEMATECH's 3D Interconnect Unit Process Development Group at the College of Nanoscale Science and Engineering Campus in Albany, New York. He obtained his BS in Chemical Engineering from the University of Alberta in 1992 and his PhD in Chemical Engineering from the University of Pennsylvania in 1999. Dr. Quon joined IBM in 2000 as a process engineer for flip-chip interconnect technology. His role evolved to a broader flip-chip interconnect integration role, leading to the successful development and qualification of the first lead-free C4 plating offering from IBM. In 2005, Dr. Quon moved to the Advanced Foundry BEOL Process Integration team, where he led the development and qualification of multiple technology nodes for Cu Interconnect.

Presentation:  

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Title:   3D IC Integration and Roadmap
     
Abstract:   TBA 
Speaker:  

Dr. Lei Fu

Bio(TBA)

Presentation:  

N.A.

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Title:   Markets and Technology Drivers for 3D IC Packaging
     
Abstract:   The success of the SMART phone has created a phenomenal growth for mobile computing platforms, which use a package-on-package (PoP) for its core processor, bottom package, to communicate with the mobile memory on the top package.   The electronics used in the SMART phone are similar to those used for tablet computers, and is projected to continue to grow at a very aggressive rate.   These mobile applications are driving a voracious appetite for bandwidth to greater than 12GB/s by 2012. In addition, it will be necessary to design the next generation of electronics to consume less power in order to extend the life of the battery. This is where the current PoP package limitations become clear and stacked 3D IC architecture has the potential to provide significant performance benefits.   One example of this technology is the wide I/O DRAM standard which enables >12GB/s performance using 50% less power, when compared with a PoP design, by using over a thousand fine pitched (40µm) through silicon vias (TSVs).   These same technology requirements are necessary for the huge processor farms that support cloud computing, which are growing at a dramatic rate each year.   It is projected that both the mobile and high performance computing markets will drive the need for low cost, high volume manufacturing of 3D IC packages. Although much progress has been made to commercialize this technology, there are still challenges with making low stress, reliable and cost effective TSVs in 12" wafers, and even larger challenges with the stacking of die with TSVs. The technology chokepoints and supply chain limitations that are slowing the introduction of 3DIC to the marketplace will be presented.
Speaker:  

Chuck Woychik

Charles Woychik
Director of Marketing and Technology
Tessera Technologies Inc., Invensas Corporation group

Charles Woychik is Director of Marketing and Technology for Invensas Corporation™, a wholly owned subsidiary of Tessera® Technologies Inc. (Nasdaq: TSRA). He draws from 25 years of experience in the area of microelectronics packaging, and his extensive knowledge of the design, materials selection and processes used for microelectronics packaging applications ranges from high-performance computer processors to low-cost mobile applications. Prior to Invensas, Chuck worked for General Electric Global Research and Advanced Semiconductor Engineering, after spending the first 18 years of his career with IBM. He holds a doctorate and Master's of Science degree in Materials Science and Engineering from Carnegie-Mellon University. He has a Bachelor's of Science degree in Materials Science from the University of Wisconsin, Madison. Chuck has numerous publications and 42 patents to his credit.

Presentation:  

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Title:   Thermo-mechanical Challenges from the best engineering practices prospective for TSV technology
     
Abstract:   TBA
 Speaker:  

Gamal Refai-Ahmed 

Presentation:  

For presentation click here.

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Title:    Inorganic/Organic Hybrid Materials for Photovoltaics on Flexible Substrates 
     
 Abstract:   TBA 
Speaker:   

Wayne Jones

Presentation:  

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Title:   Projected future Army needs and Their Implications on Packaging
     
Abstract:   TBA 
Speaker:  

Romeo Delrosario

Dr. Romeo del Rosario received his Bachelor's degree from the Catholic University of America in Washington, D.C., and the M.S.E. and Ph.D. degrees in Electrical and Computer Engineering from the Johns Hopkins University in Baltimore, MD.
He has worked as an electrical engineer at the U.S. Army Research Laboratory and its predecessor, the Harry Diamond Laboratory, since 1991. He is currently the Chief of the Electronics Technology Branch in ARL's Sensors and Electron Devices Directorate, focusing on RF front end electronics, MMIC and analog integrated circuit design, and prognostics & diagnostics. His experience spans several areas including characterization & modeling of high frequency semiconductor devices, fabrication and failure analysis of electron devices and circuits, advanced lithography, and high power microwave technology. Dr. del Rosario currently leads the Government Microcircuit and Applications Critical Technology Conference as the 2012 General Chair and recently completed service as its 2011 Technical Chair.

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 Title:   Effect of Surface Texturing on Superoleophobicity and Contact Angle Hysteresis
     
 Abstract:   Earlier we reported the fabrication of a model superoleophobic surface comprising ~7 mm tall, ~3 mm diameter pillar arrays on Silicon wafer via the conventional photolithography and surface fluorosilanation techniques. Evidence is provided that both surface fluorination and the re-entrance structure in the pillar are crucial in achieving the Cassie-Baxter state that leads to superoleophobicity. In this work, we report investigation on the effects of pillar height, size and spacing on the surface properties. Our results showed that surface superoleophobicity remains as the height of the pillar decreases from about 7 to 1 mm. This finding suggests that the abrasion resistance of the surface can be improved tremendously without sacrificing the superoleophobicity.   On the other hand, while the static contact angles remain "super" (>150°) when the pillar size and the pillar spacing vary, both sliding angle and contact angle hysteresis are found to decrease as the solid area coverage decreases. The results can be attributed to the contact line pining effect.   As the solid area coverage decreases, the length of the contact line per unit area decreases and the sliding angle and the contact angle hysteresis decrease as a result.
 Speaker:  

Kock-Yee Law

Kock-Yee Law is currently an area manager in the Xerox Innovation Group responsible for the development and delivery of next gen print surfaces and Nanotechnology enablers for the future.   Prior to that, he has done extensive research in photoconductive materials, charge-generation and charge transfer mechanistic studies of toner materials, and materials & components with controlled conductivity. He had also managed technology programs leading to technology injections into numerous products.

Presentation:  

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 Title:   Printable and Flexible Electronics: Towards Materials Development and Device Fabrication
     
 Abstract:   Nanocomposites will play an important role for developingadvancedprintable and flexile technology. Materials printing is a relativelynewtechnology and needs more characterization and optimization before useinmanufacturing operations. In the present paper, the use ofnanocompositesor materials in the area of printable and flexible technology isexamined.A variety of printable nanomaterials for electronic packaging havebeendeveloped for nano capacitors and resistors. Nanocomposites canprovidehigh capacitance densities, ranging from 5 nf/inch2 to 25nF/inch2,depending on composition, particle size, and film thickness. A varietyofprintable discrete resistors with different sheet resistances, rangingfrom1 ohm to 120 Mohm, processed on large panels (19.5 inches x 24 inches)hasbeen fabricated. Low resistivity nanocomposites, with volume resistivityinthe range of 10-4 ohm-cm to 10-6 ohm-cm, depending on composition,particlesize, and loading, can be used as conductive joints for high frequencyandhigh density interconnect applications. The paper also describes aflexibletechnology for fine line structures. A variety of materials,includingpolyimide, PTFE, liquid crystal polymer (LCP), have been used todevelopflexible packages. Flexible packages with embedded passives are alsobeinginvestigated. A key element of these flexible packages is incorporationofintegrated decoupling capacitance/resistance layers. Use ofnanomaterialsto enhance the conductivity of electrically conductive pastes,formprintable integrated resistors with controlled sheet resistance, andformcapacitors with high capacitance density will be presented.Performancecharacteristics, including both electrical and mechanical behaviorofcircuits with various levels of complexity will be presented.Collectively,the results suggest that flexible and printable materials may beattractivefor a range of applications, not only where flexibility is required,butalso in large-area microelectronics such as radiofrequencystructures,medical devices and more.
 Speaker:  

Mark Poliks

Dr. Mark D. Poliks is Director of Research and Development at EndicottInterconnect Technologies, Inc., Technical Director of the Center ofAdvanced Microelectronics Manufacturing (CAMM) and Research Professor of Chemistry, Materials Science & Engineering at the State University of New York at Binghamton. Previously he wasManagerof Organic Materials & Processing at the IBM Corporation,Microelectronics Division.

Presentation;  

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Title:   Interconnection Technologies: Gate Keepers of Electronic Performance, Past Present and Future
     
Abstract:   Though not always recognized, the age of electronics is actually now well into its second century and increasingly electronic interconnections being recognized as the important gatekeepers of electronic performance and reliability. As a result, there has been increased attention given to that which was once considered a prosaic element of the electronics system. This presentation will look at the hierarchy of electronic interconnections from chip to system and review some of the changes that are taking place which are blurring the once sharp lines that defined the hierarchy of electronic interconnection. Topics touched on will include: 3D, printed electronics, elastronics and solderless assembly
Speaker:  

Joseph Fjelstad

Joseph Fjelstad, founder and president of Verdant Electronics is a 40 year veteran of the electronics interconnection industry and serial entrepreneur. He is also an inventor and author/coauthor of several books including the just released 4th edition of Flexible Circuit Technology. Fjelstad is also an industry magazine columnist, commentator, lecturer and keynote speaker.

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Title:   Continuous Recrystallization of Pb-free Solder Joints in Thermo-mechanical Fatigue
     
Abstract:   The recrystallization of beta-Sn is an important microstructure change and has profound impact on solder joint deformation behavior and fatigue life. The newly formed grain boundaries enable grain boundary sliding, which is absent in as-solidified solder joints. Accumulation of grain boundary damages during thermo-mechanical fatigue (TMF) results in the initiation and propagation of fatigue cracks along the recrystallized grain boundaries, and eventually leads to intergranular fracture. In this study fatigue tests were performed on various SnAgCu solder joints. The recrystallization behavior was seen to depend on fatigue loading condition, alloy composition and the thermal history of solder joints, such as isothermal aging. The results also suggested that the recrystallization behavior might depend on the morphology and distribution of secondary precipitates.
Speaker:  

Liang Yin

Liang Yin received the M.S. degree in mechanical engineering in 2003 and the Ph.D. degree in materials engineering in 2005, both from the State University
of New York at Binghamton. He is currently a Process Research Engineer at Universal Instruments. His research is focused on solder joint reliability, such as reactive wetting, phase transformation and microstructure of solder alloys.

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Title:   Affordable High Performance RF Module Integration Methodology
     
Abstract:   A commercially viable integration methodology for high frequency application is presented. It is called RF Chips Last. By exploiting the commercial capabilities, it provided a generic RF integration strategy with more affordable, high performance, highly integrated, and RF module fabrication. The methodology is parsed up into basically four different blocks to solve for: Interconnect Substrate, Device Attach, Assembly, and Thermal Management. This process improves RF module yield substantially due to the fact that the RF substrate and chip can be modeled/tested separately before they are being assembled compared to the traditional first chip assembly process. Reliability and reproducibility are another advantages of the proposed assembly technology that will be addressed.
Speaker:  

Yongjae Lee

Yongjae Lee works at RF Instrumentation and Systems Lab in GE Global Research, located in Niskayuna, NY. He has been working for 3 years executing a variety of projects related to RF, mmWave technologies. Before he joined GE, he worked at Ethertronics, in CA as an antenna engineer, developing various types of customized antennas for mobile device applications. His expertise areas are RF/mmWave circuit design, antenna design, and 2D/3D electromagnetic numerical analysis of passive RF components, system, including MEMS devices. Multiphysics analysis is also a part of his expertise. He earned Ph.D and M.S degrees in Electrical and Computer Engineering from University of Colorado, Boulder, 2006 and 2004, respectively.

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Title:   Robust Assembly of Fine Pitch Through-Molded-Via (TMV) Package-on-Package (PoP) Devices
     
Abstract:   Consumers continually drive electronics packaging engineers to design for portability, higher functionality, and smaller form factor, all while maintaining low manufacturing cost. This translates to managing smaller component geometries that are mounted to the board in higher densities, which generally requires more accurate processes with tighter tolerances to satisfy end of line yield targets. Package-on-Package technology offers several advantages by increasing density and functionality while maintaining footprint. Newer, POP devices now in manufacturing include Through-Molded-Vias which are designed to minimize the extent of warpage, a major concern in the robust assembly of stacked devices.

This investigation will highlight the impact of process variables on the robust assembly of fine pitch TMV PoP devices. Parameters will include stencil printing and material selection for bottom package attach; flux and solder paste dipping parameters and material selection for stacked packages; and reflow profile.

Speaker:  

Brian Roggeman

Bio(TBA)

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Binghamton University State University of New York
PO BOX 6000   Binghamton, NY 13902-6000

Last Updated: 4/11/12